An antifuse is a device commonly used to create a programmable connection between two nodes of an integrated circuit. Antifuses are used in a wide variety of types of integrated circuits, as for example in programmable read only memory devices (PROM's), programmable logic devices (PLD's), and programmable gate array logic devices. An antifuse typically includes two conducting or semiconducting electrodes or contacts and an insulating or dielectric interlayer material that lies between the two electrodes. The initial unprogrammed condition of an antifuse is an open circuit. During programming of the antifuse, the insulating interlayer material is broken down at selected points to electrically connect the contacts together through the insulating interlayer material.
Typically, antifuse devices are programmed by electrical or optical methods. Electrical programming of antifuses of an integrated circuit device may be achieved after the integrated circuit device has been fabricated and packaged. In contrast, optical methods typically must be employed during fabrication. Current state of the art optical programming methods use high powered lasers which can rapidly write a small area at speeds of up to on the order of 1000 pulses per second. Thus, optical programming methods may allow high speed programmability.
Antifuse devices may be disposed on the surface of a semiconductor substrate of an integrated circuit. Alternatively, antifuse devices may be disposed in layers above the surface of the semiconductor substrate of the integrated circuit. For example, metal to metal antifuse devices are commonly used to create programmable links between two metal interconnect layers in an integrated circuit. Metal to metal antifuses typically include an interlayer of amorphous silicon disposed between first and second layers of refractory metals.
FIG. 1 shows a typical prior art antifuse device 100. Antifuse device 100 includes a field 102. Field 102 provides a first programmable contact of antifuse device 100. Field 102 may be a metal interconnect, a gate of a transistor, or any other conducting or semiconducting material. A dielectric layer 104 is generally formed over the field 102 to electrically insulate the field 102 from subsequently deposited conducting structures. The dielectric layer 104 is typically formed from silicon dioxide (SiO.sub.2) or another appropriate insulating material. Vias 106 are then typically etched into the dielectric layer 104.
After the vias are formed, an insulating or dielectric interlayer 110 is conformally deposited over the wafer surface thereby covering the bottom and sidewalls of via 106. The antifuse interlayer 110 is typically formed from either amorphous silicon or polysilicon. A conducting layer 114 is then deposited over the insulating interlayer 110. The conducting layer 114 provides a second programmable contact of the antifuse device 100. The conducting layer 114 is typically formed from a refractory metal such as, for example, titanium (Ti), tungsten (W), tantalum (Ta), or molybdenum (Mo). Refractory metals form silicides with silicon in a reaction known as silicidation which is further described below. A conducting plug material 116 is formed over the conducting layer 114 to fill in the via 106. The conductive plug material 116 is typically formed from a metal.
During electrical or optical programming of the antifuse device 100, metal atoms from the conducting layer 114 and the field 102 are diffused into the insulating interlayer 110 to form conducting paths 118. For example, if the antifuse device 100 is a metal to metal antifuse utilizing amorphous silicon for the insulating interlayer 110 and a refractory metal for the conducting layer 114, thermal energy generated by electrical or optical energy results in silicides forming in the insulating interlayer 110, which silicides form conducting paths 118 between the field 102 and conducting layer 114. A silicide of a metal is formed when metal is alloyed on a silicon surface. Alloying causes inter-diffusion of the metal and the silicon surface.
A problem with conventional antifuse device 100 is that the conductive paths 118 formed through the insulating interlayer 110 are not confined to the via region 108. Conductive paths 118 may also be formed outside of via region 108 in a crawl-out region 112. Therefore, the salicidation reaction may not be localized. Conductive paths formed in crawl-out region 112 may cause degradation of performance integrity or failure of an integrated circuit which includes antifuse device 100.
What is needed is an antifuse device in which formation of conductive paths through the interlayer material is confined within a finite and predictable region. What is further needed is an antifuse device in which conductive path formation is confined to a via region of the antifuse device.
These and other advantages of the present invention will become apparent upon reading the following detailed descriptions and studying the various figures of the drawings.